System Verilog

Objective

The objective of the course is to provide an understanding of different features of System Verilog programming for Verification and Testing.

Course Description
•    Introduction to System Verilog HDVL
•    Improved data types
•    Operators
•    Oops Concept
•    Different test generation approach 
•    Basic components of testbench architecture in System Verilog

Learning Outcomes
After successful completion of the module, the students shall be able to:

1.    Will be able to understand the features of System Verilog
2.    Understand System Verilog syntax, data types, and key language enhancements over Verilog.
3.    Apply object-oriented programming concepts to build reusable verification components.

Reading List:

System Verilog for Verification: A Guide to Learning the Testbench Language Features
By Chris Spear & Greg Tumbush