Objective
The objective of the course is to provide an understanding of the techniques essential to Verilog programming for Verification and Testing.
Course Description
• Introduction to Verilog HDL & Hierarchical Modeling Concepts
• Lexical Conventions & Data Types
• Modules, Ports
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Objective
The objective of the course is to provide an understanding of the techniques essential to Verilog programming for Verification and Testing.
Course Description
• Introduction to Verilog HDL & Hierarchical Modeling Concepts
• Lexical Conventions & Data Types
• Modules, Ports and Module Instantiation Methods
• Modelling methods.
• Design Verification using Test benches
Learning Outcomes
After successful completion of the module, the students shall be able to:
1. Write Verilog code, compile, simulate and execute any Digital Circuit
2. Able to perform verification and testing
Reading List
1. Verilog HDL, 2/E By Samir Palnitkar, Pearson Education
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