loading...
About K-VLSI Design Skill Program

The Industry and Govt.of Karnataka acknowledges the pressing need to address the increasing demand for skilled professionals in the field of VLSI (Very Large Scale Integration) Design. With rapid technological advancements, VLSI plays a crucial role in sectors such as telecommunications, automotive, healthcare, and consumer electronics. However, there is a significant shortage of trained individuals possessing the necessary knowledge and expertise in VLSI Design.

To tackle this critical requirement, we are delighted to launch the Next Generation K-VLSI Design Program, in collaboration with the MINRO Center at IIIT Bangalore, IESA, and SAFL. This intensive 6-9 month skill development pilot program is specifically tailored for VLSI Design, aiming to equip students with the essential skills and make them job-ready for the thriving ESDM industry.

Course & Program Outcome

Industry-relevant VLSI engineering skills

Real-world VLSI project execution

Well defined design outcome

Active interaction with the industry experts

Industry training or internships

100% Placement assistance

Certification from IIIT-B and IESA

Networking Opportunities

Eligibility Criteria

Engineers from Electronics, ECE, CS, IT and related engineering branches

  • Engineering students in their 7th semester, studying at a UGC/AICTE-approved college or university within Karnataka, are eligible to apply.
  • Students who have completed (or passed out from) their engineering in 2020 onwards till 2023
  • Alternatively, 7th-semester students with Karnataka domicile who have pursued their engineering studies outside the state are also eligible.
  • Classes start on 17th Feb 2025
Eligibility Criteria
Convocation 2023

Program Fee: The overall value of the program is INR 2,50,000+. However, the shortlisted candidate will only pay 15000 + GST

Application Process

1
Submit Application (13 Nov, 2024 - 01 Jan, 2025)
Tell us a bit about yourself and why you want to join
Submit Application
2
Admission Test & Interview (3 Jan, 2025 - 22 Jan, 2025)
Clear the Aptitude, Digital & C Language based admission test and have a personal interview with our interview panel
Submit Application
3
Admission Letter (25 Jan, 2025)
Shortlisted candidates would be offered the admission letter
Submit Application

NOTE:- Decision taken by Futurewiz Management in regard to test/interview/selection - will be final

Benefits of the Course
  • Industry-relevant VLSI engineering skills
  • Real-world VLSI project execution
  • Well defined Design Outcome
  • Active interaction with the industry experts
  • Industry training or internships
  • 100% Placement assistance
  • Certification from IIIT-B and FutureWiz
  • Networking Opportunities
K-VLSI cohort 2 Timeline 2024
TIMELINE TIMELINE
Course Curriculum

1SOC Architecture Introduction

2Digital

3Analog Design Introduction

4Design Flow

5Design Architecture, RISC-V & ARM

6 Verification - Introduction

7Introduction to Emulation

8 DFT Basics (Scan, JTAG, BIST)

9Introduction to Synthesis & Timing Constraints

10Placement, Routing & CTS

11Validation

12 C and OOPs Basics

13Verilog & System Verilog

14Embedded Software

15Python Scripting

16Mini Projects (frontend & backend)

17 Major Project (frontend/backend)

18Summary

Contact Us
Get in Touch

We really appreciate you taking the time to get in touch. Please fill in the form for any further queries.

KARNATAKA DIGITAL ECONOMY MISSION
KEONICS, 27th Main Rd, 1st Sector, HSR Layout, Bengaluru - 560102, Karnataka