About the Course

• The course starts with Verilog language semantics, syntax and simulation using Verilog based testbench.
• SystemVerilog language semantics and simulation fundamentals such as arrays, Inter-Process communication, events and race conditions, which feed into closely related entities in program block, clocking block, and interfaces.
• Professionals will teach how to develop a complete verification environment by building flexible testbench components via the use of virtual interfaces, classes, mailboxes, dynamic arrays, and queues, etc.
• Functional coverage in the form of covergroup, coverpoint and bins will round up the development of a complete verification environment. You will become familiar with the flexibility of an OOP-centric technique, the power of constrained random verification and the use of functional coverage tools to ensure the success of a verification project.
• Concepts taught in class are reinforced with peculiar examples. In addition to in-class hands-on labs, you will work on a required project to build an advanced OOP testbench and verification environment, with transaction-level and layered architecture.
• Professionals will create a test plan, develop an OOP based verification environment, perform functional coverage.

Course Objectives

• This course builds strong foundation in SystemVerilog to become proficient in Verification Using UVM (Universal Verification Methodology).
• Gain familiarity with working in a SOC design flow and architecture

Course Duration : 9 weeks

Who should go for this course?

• Course is targeted to experienced VLSI engineer looking to enhance their job opportunities and skill sets.
• Non-VLSI professionals who have a passion to learn VLSI.

Pre-requisites

• Knowledge of digital electronics, basic programming fundamentals, C/C++ and some hardware verification experience.