- This course builds strong foundation in SystemVerilog to become proficient in Verification Using UVM (Universal Verification Methodology).
- Gain familiarity with working in a SOC design flow and architecture
Course Duration : 9 weeks
Who should go for this course?
- Course is targeted to experienced VLSI engineer looking to enhance their job opportunities and skill sets.
- Non-VLSI professionals who have a passion to learn VLSI.
- Knowledge of digital electronics, basic programming fundamentals, C/C++ and some hardware verification experience.