Learning Outcomes:

• Exploration of basics of Hardware Description Languages.
• Learning more about the different types of HDLs such as Verilog and VHDL.  
• Gaining a better understanding of the significance and Applications of HDLs.

Most people would agree that the basis of any civilization or society is language. Electronics professionals also use languages unique to their community, which is akin to its own society. VHDL and Verilog are two of these industry-specific (hardware description) languages. Both are regarded as general-purpose digital design languages, although Each has little distinctions and advantages over the other.

What are the HDLs?

Hardware description languages (HDLs) are used to define or explain the behavioral properties of digital logic circuits.  The analysis and simulation of an electronic circuit is made possible by a hardware description language, which permits a precise, formal description of an electronic circuit.

Additionally, it enables the creation of a netlist from an HDL description (a description of the physical electronic components used and how they are connected), that can be arranged and routed to construct the group of masks required to make an integrated circuit.

HDLs are used to build digital circuitry such as computer chips, motherboards, processors, and other types of hardware.

Although there are many HDLs, but VHDL and Verilog are the most widely used. These languages are supported by most CAD tools on the market.

VHDL: History and Applications

VHDL stands for Very High-Speed Integrated Circuit (VHSIC) Hardware Description Language, which is used to describe the behavior of digital circuits or can be used to create or implement hardware for digital circuits or systems. Mixed-signal and digital systems, such ICs (integrated circuits) and FPGA (field-programmable gate arrays), are expressed using VHDL in EDA (electronic design automation).

In the 1980s, the VHSIC (Very High-Speed Integrated Circuit) program was launched by the US DoD (Department of Defence) with the aim to design high-speed ICs. A variety of hardware development firms began creating their own HDL for their ICs. Every company had its own unique HDL. The issue thus arose from the inability of all these various companies to share their code and designs. Eventually, every company sent a designed chip design with a different HDL to DoD. Therefore, it was necessary to standardize hardware description language for the design, documentation, and verification of digital circuits and systems.

In 1985, Under a DoD contract, IBM, TEXAS INST., and Intermatrix developed the initial version of VHDL 7.2. Which later in 1987, was standardized by IEEE with IEEE 1076 standard. After some modification, VHDL received the new standard IEEE 1164 in 1993, which is now widely used.

Several child standards were introduced in addition to IEEE standard 1164 to increase the language's capability. Better handling of real and complex data types has been added in IEEE standard 1076.2. To simplify arithmetic operations on vectors, IEEE standard 1076.3 introduced signed and unsigned types.

The next revision of the standard, known as VHDL-2006, was accepted in June 2006 by Accellera's VHDL Technical Committee, which was compatible with the previous versions of VHDL. Then VHDL-2008 came up to address more than 90 problems that were found during the VHDL-2006 trial period and added improved generic types.

Key Benefits of VHDL

• It supports several design strategies, including Top-down and Bottom-up approaches.
• VHDL projects can be generated for one element base and subsequently ported to another element base because of the portable nature of VHDL.
• Better design management is also an advantage of VHDL.
• Considering that VHDL is a dataflow language, every statement may be considered for execution at the same time.
• It strongly encourages sharing and reusing of code to make VHDL projects multipurpose, it means the computation block can be used in numerous other projects after we build the project just once.

Limitations of VHDL

• It's harder to learn VHDL.
• It necessitates a thorough understanding of the language's syntax and code structure.
• Some of the VHDL programs are non-synthesizable.
• Visualizing and troubleshooting a design is more challenging in VHDL.

Due to the capabilities of addressing the VHDL limitations, Verilog is popularly used by most industry experts. 

Verilog: History and Applications

Verilog was initially started by Gateway Design Automation Inc. around 1984. It took till 1990 for Verilog to be a standardized language. The First Verilog simulator came up in 1985. It added up XL Algorithm as a result it was a very efficient method for gate-level simulation.

Around the late 1990s, Cadence purchased Gateway Design Automation Inc. and became the possessor of the Verilog language and simulator. Synopsys at the same time was marketing design methodology using Verilog. Same time Cadence understood Verilog needed to be opened in the market for it to evolve. So, it created Open Verilog International (OVI). This opened the language. OVI soon became vendor independent. But most organizations working with Verilog wanted to customize it. Therefore in 1994, IEEE 1364 working group was formed to convert OVI into an IEEE standard.

Soon after going into the 1990s many companies began working on Verilog simulators. VCS most popular, Verilog compiled simulator from Chronologic Simulation, its compile time was substantial, but simulation execution was faster.

The IEEE 1364 working committee in 1993 onwards further standardized Verilog. This now contained the language and came to be known as IEEE std. 1364-1995. In the subsequent years, many features got added and were successful in solving many problems. In 2001 the new version of Verilog came up to be known as IEEE std 1364-2001.

Benefits of Verilog

• As compared to other HDLs, Verilog generates higher-performance designs.
• Verilog is supported by many synthesis tools.
• Verilog has shorter lines of code compared to VHDL for the same design.
• To explain complex circuits or systems, it offers high-level language constructs.
• It is easy to optimize the designs.
• It uses C-like syntax, hence easy to understand.
• Design is device independent. The design transition from PLD to ASIC is seamless.

Limitations of Verilog

• Traditional design methods are used to create the control logic.
• There is a problem with portability.
• For schematic capture design, the simulation environment is different.

Comparison of VHDL with Verilog

Conclusion

In this article, a brief discussion of the hardware description languages and their functional difference is presented. VHDL and Verilog are the two popular HDLs used for the modeling of digital designs. Our discussion was centered around both languages' history, evolution, benefits, and limitations. There are no major differences between VHDL and Verilog observed. In conclusion, there are many different viewpoints regarding the superiority of one language over another, but ultimately, it just boils down to personal preference.