UVM – Universal Verification Methodology is a verification methodology that uses the system Verilog to have a robust and reusable verification environment. It was established by Accellera and jointly developed by Cadence and Synopsys. It is mainly derived from the OVM(open verification methodology). On May 17, 2010, UVM 1.0 was made available.Its Class Library offers the building blocks required to swiftly create well-designed and reusable verification components and test environments.System Verilog is used as the language for it.  UVM is now supported by all three of the major simulation providers (Synopsys, Cadence, and Mentor), which was not achievable with earlier verification methodologies such as OVM, VMM and eRM.

Universal Verification Methodology is an open-sourcemethodology,It is primarily intended for verification IP and testbench components, enabling more portable and universal test benches and verification codes.Each verification component adheres to a uniform architecture and a full set of elements for simulating, testing, and gathering functional coverage.The verification environment generated using UVM remains the same regardless of the vendor, while the verification environment developed using System-Verilog may vary depending on the implementer.

Requirement and Uses:

As the industry is growing and technologies are evolving day by day, complex designs are the real challenge for any verification engineer to verify its functionality. It’s a verification engineer’s responsibility to make sure the design is bug-free before it’s tape out. Verification is the most time-consuming process in a chip’s manufacturing cycle right from day one. Missing a bug in the initial stage and capturing it in its final stage will cause a lot of issues financially as re-spin is a very expensive process to do.

Figure1: UVM Testbench Architecture

System Verilog would help engineers to verify super complex designs with a lot of flexibility with object-oriented support.  Along with OOPs it also has some verification-targeted features like functional coverage, Assertions, Random constraints, etc. These features make the language very powerful and handy to use and have the potential to reduce verification time and effort.

UVM with the help of system Verilog would make the testbench environment more streamlined and reusable. A general UVM  testbench architecture is illustrated in fig 1.

Features of UVM:

• UVM has a lot of powerful in-built macros which are used by the engineers to make more efficient codes.
• UVM has factory methods to override its existing components with the newly updated components in various environments. It will boost up code reuse-ability.
•  The other main advantage of UVM is TLM ports. It is used to perform packet-level transactions among the UVM components.
•  TLM provides overall packet-level abstraction in the verification environment.
• UVM phases provide synchronization between the UVM components. This allows the environment to work properly without any ambiguity between the components.
• UVM has a built-in register model which is helpful in performing back door access and keeping track of the register’s current status.
• UVM configuration database provides some inbuilt methods to share common variables/data between the components.

Comparison of System Verilog and UVM:

• In UVM, ports and exports are used for communication, while mailboxes are used for the same in the system Verilog.
• UVM was used to create a robust and interoperable test bench.
• Several built-in UVM functions can be used directly from the libraryWe must create our own logic codes in System Verilog for operations like copy, print, and pack, among others.
• Compared to System Verilog, UVM requires less time to construct a testbench.

Benefits of Universal Verification Methodology:

Conclusion

Compared to UVM, System Verilog hasfewer macro and function capabilities and no built-in reflection.Although some SystemVerilog capabilities may have been supplied as library functions.UVM combined with the system Verilog makes the verification work easier. The UVM testbench Architecture is the most followed verification architecture in the semiconductor industry. Building a reliable and reusable verification environment is not simple. A suitable framework and assistance from the base classes are required to develop it.UVM offers a comprehensive collection of the basic class libraries and features needed for effective verification. It provides a strong, simple-to-understand environment that may be used by other companies.While the industry kept on evolving the standard system Verilog and UVM created a benchmark in the semiconductor industry with their unique and powerful features.UVM offers a higher level of abstraction, therefore it takes less time to construct a testbench using it. The functional coverage is increased by virtually completely covering all scenarios and edge cases.