Verilog is a hardware description language, rooted back in 1984 by "Gateway Design Automation". A HDL (hardware description language) is a language which is serves the purpose of designing hardware.

Wherein "C" is programming language, invented back in 1972 by "Dennis Ritchie" which serves the purpose of software programming.

Since most of the constructs of the Verilog were derived from C language, the basic syntactical data base of both the language is same. Verilog uses mostly same constructs and lexical which is used for programming in the C language.

Let's begin with understanding basic data types that had been inherited by Verilog from C language:

Integer eg. 1, 2..n
Float eg. 1.0, 2.1..n.n

These were two basic data types used to represent number in absolute and real type format which had been transformed to:

Integer eg. 1, 2 ..n
Real eg. 1.0, 2.1 ..n

Basic idea of saving time and reducing redundancy of code by implementing functions remain same. In Verilog also, there is a freedom to write function. There are minor changes like "{ /}" which were used to group the statements together and bind to a different scope had been replaced by "begin/end" as below:

function int sum(integer a, integer b)
beginsum = a+b;
end

In both the languages output of the function is returned by the call of the function via function name. Just a slight change is return statement is omitted in verilog, output could be directly assigned.

The looping statements also remains same, the basic idea of looping via "for", "while" is syntactically same. "for" loop uses same three parameters as in C language:

for(init; break ; increment_val)
begin
// code
end

where "init" is the initialisation condition, "break" is the break condition to exit the looping, while "incremented_val" is the loop iteration value.

Verilog also offer conditional statements like "if/else" and "case". Both statements serve same purpose and syntax in verilog as in C language. All the combinations of if/else like ladder type and nested structures are possible in verilog too. For eg.:

if(condition)
begin
//Code
end

else if(condition)
begin
//Code
end

else
begin
//Code
end

Since verilog is an HDL, it tells how hardware would be developed and behaves physically rather than C programming language which is used to configure already developed hardware; verilog offers few more constructs for timing/delay and parallel processing which were not present in C language.

So, overall most of the lexical of verilog are derived from C language and hence are similar in use and application.